1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device which is operated by a plurality of power source voltages such as a voltage at the time of reading data like a nonvolatile semiconductor memory, and a higher voltage at the time of writing and erasing data, and its manufacturing method.
2. Description of the Related Arts
In a nonvolatile semiconductor memory device, data writing and erasing operations are performed by a high voltage. On the other hand, a nodal reading operation is performed by a low voltage as compared with the writing and erasing operations. Due to this, a thick gate insulating film, which can withstand a high voltage, is needed in the elements used in writing and erasing in order to ensure reliability. In contrast, since a lower voltage is needed in the elements used in reading, a thin gate insulating film may be used. Rather, there is a case in which the thin gate insulating film may be used in order to achieve a high performance such as a high speed operation.
Therefore, there is a case in which it is necessary to have two or more kinds of different thickness gate insulating films and element separation insulating films formed in one device.
FIGS. 28 to 32 are cross sectional views showing a conventional method for manufacturing a nonvolatile semiconductor memory device. This nonvolatile semiconductor memory device includes a high voltage withstanding transistor area (hereinafter called "high voltage withstanding area"), transistor areas other than the high voltage withstanding area ("low voltage withstanding area"), and a memory cell transistor area (hereinafter called "cell area").
First, as shown in FIG. 28, first to sixth element separation insulating films 2a to 2f are formed on a surface of a p type silicon substrate 1 having a cell area 1a, a high voltage withstanding area 1b and a low voltage withstanding area 1c. An oxide-nitride film 3 having a thickness of about 100 angstroms to serve as a gate insulating film of the cell area 1a is formed on the surface of the p type silicon substrate 1 positioned among these element separation insulating films 2a to 2f. Thereafter, a first polycrystalline silicon film 4 is deposited on these element separation insulating films 2a to 2f and the oxide-nitride film 3.
Next, as shown in FIG. 29, a first resist pattern 5 is formed on the first polycrystalline silicon film 4. Thereafter, the first resist pattern 5 is used as a mask to perform etching, whereby the first polycrystalline silicon film 4 positioned on a floating gate separation area 6 of the cell area 1a is removed.
Thereafter, as shown in FIG. 30, the first resist pattern 5 is separated. Next, an ONO (oxide-nitride-oxide) layer film 7, serving as an insulating film between a control gate and a floating gate, is formed on a surface of said first polycrystalline silicon film 4.
Next, as shown in FIG. 31, a second resist pattern 8 is formed on the cell area 1a. Thereafter, the resist pattern 8 is used as a mask to perform etching, whereby the ONO layer film 7 and the first polycrystalline silicon film 4 are removed. Next, the oxide-nitride film 3, which is positioned on each of the high voltage withstanding area 1b and the withstanding low voltage area 1c, is etching-removed with NH.sub.4 F, thereby exposing the surface of the p type silicon substrate 1.
Thereafter, as shown in FIG. 32, the second resist pattern 8 is separated. Next, an oxide film 9 having a thickness of about 250 angstroms to serve as a gate insulating film of the high voltage withstanding area 1b is formed on the surface of the exposed p type silicon substrate 1.
Thereafter, a second polycrystalline silicon film 10 is deposited on each of the ONO layer film 7, the third to sixth element separation insulating films, and the oxide film 9.
In the above-mentioned conventional nonvolatile semiconductor memory device and its manufacturing method, the third and fourth element separation insulating films 2c and 2d, which are positioned at the high voltage withstanding area 1b, become thin. This is because the third and fourth element separation insulating films 2c and 2d are simultaneously etched when the oxide-nitride film 3 is etched as shown in FIG. 31. As a result, a reverse field voltage is lowered in the third and fourth element separation insulating films 2c and 2d, and there occurs a problem in providing a required high withstanding voltage to the high voltage withstanding area 1b.
As a method for preventing the reverse field voltage from being lowered, it can be considered that thick impurity material is implanted to the p type silicon substrate 1, which is positioned just under the third and fourth element separation insulating films 2c and 2d. However if this method is used in a minute element, deterioration of the narrow channel effect of the transistor occurs by exudation of impurity material, and a reduction of withstanding voltage of the surface of the high voltage withstanding element occurs. Therefore, the above-mentioned problem cannot be solved by this method.
Moreover, in the process of exposing the surface of the p type silicon substrate 1 of each of the high voltage withstanding area 1b and the low voltage withstanding area 1c, as shown in FIG. 31, the second resist pattern 8 is directly formed on the ONO layer 7 film of the cell area 1a. Due to this, the ONO layer film 7 is polluted by the resist, and the film quality of the ONO layer film 7 is deteriorated. Due to the polluted ONO layer film 7, there are problems in insulation breakage of the nonvolatile semiconductor memory device and deterioration of data storing characteristics. As a result, reliability of the memory cell is lowered.
Furthermore, since the oxide nitride film 3 is used as a gate insulating film of the memory cell transistor in accordance with a requirement for high voltage withstanding and high reliability, a white ribbon (SiN), which is not fully removed, is left on the surface of the p type silicon substrate 1 of each of the high voltage withstanding area 1b and the low voltage withstanding area 1c when the film 3 is etching-removed. The white ribbon becomes a problem particularly in the high voltage withstanding area 1b. More specifically, by the white ribbon, as shown in FIG. 32, the withstanding voltage of the gate insulating film 9 formed in the high voltage withstanding 1b is deteriorated, and breakage of the insulating film is caused when the high voltage is applied to the gate insulating film 9. Then, reduction of yield occurs.